This invention pertains generally to the field of high performance switching, including switches, switch systems and networks, and interconnect and addressing techniques suitable for implementing very high performance switching functions such as those defined in the Fibre Channel standards.
The need for high performance switching solutions continues to grow in the fields of computing and data handling systems. Examples of such systems include interconnecting computers and high-performance storage devices, interconnecting computers in a multiple-computer operating environment, and anywhere else where multiple high-speed data interconnections must be established between designated nodes or groups of nodes in a data handling network. Higher bandwidth and greater switching flexibility are prime concerns for switches and devices to be used in such systems.
The Fibre Channel standard, ANSI X3.T11, is intended to address these concerns. The Fibre Channel standard itself broadly defines classes and standards of performance, but does not dictate the implementation technologies to be used in providing these functions. A particular design of a switch to implement Fibre Channel functions is referred to as the xe2x80x98fabricxe2x80x99 of the switch.
Most presently available switch fabrics do not implement all of the Fibre Channel functions. There are a number of reasons for this, some technological and some economic. For some applications only a subset of the Fibre Channel functions are needed. But in other cases, a larger set of Fibre Channel functions would be desirable, but the cost and technological complexity of implementation remain as formidable hurdles.
In commonly-owned copending U.S. patent application Ser. No. 60/098742 filed Sep. 1, 1998, entitled HIGH PERFORMANCE SWITCHING, certain methods and switch configurations for providing high performance Fibre Channel or other switching systems are described. Those systems are based on unique switch chassis, and unique methods of interconnecting the chassis to create larger networks. The method of interconnecting chassis in that patent application might be termed xe2x80x9cmultistagingxe2x80x9d, because it provides for the interconnecting of individual switch chassis in preferred ways to achieve larger networks.
The present invention provides further improvements in high performance switching networks and methodology, by improvements in switching modules and interconnections thereof within a switch chassis to achieve higher performance, reduced complexity and greater flexibility.
It is conventional in prior art high performance switch chassis try to make use of a number of similar switch modules, and to provide means for interconnecting them on a printed circuit board or otherwise within a chassis. Often the switch modules may consist of a custom switch modules with a given number of input or output ports, for example 2, 4 or 8. Ideally, most or all of the custom switch module is implemented in single ASIC (application-specific integrated circuit), with additional supporting elements or chips as needed. Depending on which Fibre Channel functions are being implemented, it may be necessary in such prior art systems to provide a number of different custom switch module and ASIC types, to cover different types of Fibre Channel Ports. The custom switch module can generally handle requested switch connections within itself and involving its own ports. To create a switch chassis product with a more useful number of channels, for example 32, 48 or 64, it is desirable to somehow interconnect a number of such custom switch modules within the chassis.
The conventional way of doing this is to provide a high-speed bus, often referred to as a backplane, which interconnects all the custom switch modules. A fabric controller may also be programmed to direct traffic between custom switch modules according the particular requested switch connections. It is readily apparent that in such systems the bandwidth of the backplane and the operation of the fabric controller are critical. In practice, the backplane becomes the limiting factors in terms of chassis channel count, performance, and cost. In such prior art systems, attempts to increase the number of channels in a chassis quickly leads to high demands on the backplane and fabric controller, in terms of technological limitations, complexity and cost. These factors have effectively limited the number of channels in prior art switch chassis design, if any reasonably high data rates are to be maintained.
The present invention provides further improvements in high performance switching networks and methodology, and for providing a practical implementation of Fibre Channel protocols. The present invention achieves this through a method referred to herein as microstaging.
According to one aspect of the invention, the present invention provides a single fabric element, typically a single ASIC. The links between all of the ports of the ASIC are internal to the ASIC. This fabric element can be used in multiples to provide a high performance switching chassis of a significantly larger number of ports than is achievable with the prior art techniques.
According to another aspect of the invention, the fabric element ports each have a unique local routing table. This avoids the need for a global routing table for ports as is provided in the prior art. This also permits addressing and routing from port to port within the fabric element without need for look-up references from off the fabric element, thereby contributing to speed.
According to another aspect of the invention, frame transfer decisions are made using transmitter frame tags based on transmitter need and pulling frames, rather than receiver pushing frames.
According to another aspect of the invention frame steering is based on either parsed frame destination address fields for high scalability systems, or destination address field value for aliasing steering, with both methods available concurrently at any port. The steering logic may thus provide complete hardware routing of both unicast and multicast functions.
According to another aspect of the invention, a method of hard zoning is provided by setting permission bits in steering logic, so that frames may be blocked from certain destinations.
According to another aspect of the invention, a plurality of fabric elements make up a switching chassis, or network box, by unique link interconnect techniques. This avoids the problems associated with backplane bus structures. The link interconnection techniques of the present invention allow cascade, mesh microstaging, and combinations thereof. According to the microstaging aspect of the invention, a predetermined number of fabric elements use a predetermined number of their ports as channel input/output connections for the switching chassis. Preferably, these fabric elements use half of their ports for this purpose, with the remaining half used for link interconnection. In addition, for switching chassis with larger numbers of ports, some fabric elements are used only for interconnecting the fabric elements which serve as channel ports.
According to a presently preferred embodiment of the invention, a 16-port fabric element is provided, and microstaging interconnections are provided to create 32 channel, 64 channel or 128 channel switching chassis. In addition, the 128 channel microstaged switch chassis embodiment can be extended to support 256 channels, which corresponds a the full Fibre Channel Domain.
These and other features and advantages are provided with the present invention, as illustrated in the detailed descriptions of the preferred embodiments which follow.